Extend Force-directed Scheduling for System-level Synthesis in Timeconstrained System-on-Chip Design

Authors:
Qiang Wu;Renfa Li;Wei Wang;Wei Xie;Jinian Bian;Yunfeng Wang;Haili Wang
Affiliations:
Hunan University, Changsha, China;Hunan University, Changsha, China;Hunan University, Changsha, China;Hunan University, Changsha, China;Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;Tsinghua University, Beijing, China
Venue:
ICESS '05 Proceedings of the Second International Conference on Embedded Software and Systems
Year:
2005

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A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs

Journal of Systems Architecture: the EUROMICRO Journal

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Abstract

Scheduling time-constrained task graph to minimize resource requirement is a common and important problem in system-level synthesis (SLS) for system-onchip (SoC) designs. Many algorithms have been proposed to address this issue. In this paper, an extended scheduling algorithm based on force-directed heuristic is presented, which adopts a notion of continuous time rather than a notion of discrete time in high-level synthesis (HLS). Polynomial arithmetic is employed to calculate the force function and its extremal points. Preliminary experimental results show the feasibility of the proposed algorithm.