Topology-aware tile mapping for clusters of SMPs

Authors:
Daniel Chavarría-Miranda;Jarek Nieplocha;Vinod Tipparaju
Affiliations:
Pacific Northwest National Laboratory (PNNL);Pacific Northwest National Laboratory (PNNL);Pacific Northwest National Laboratory (PNNL)
Venue:
Proceedings of the 3rd conference on Computing frontiers
Year:
2006

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Abstract

We propose a technique to optimize the performance of applications using distributed dense arrays and characterized by a nearest-neighbor communication profile by exploiting the topology of SMP clusters. The topological information is used to map array tiles to processors to reduce network communication and improve utilization of shared memory for inter-process communication. The potential benefits of using the SMP-aware mapping are demonstrated through a simulation, as well as a real application solving a wind-driven ocean circulation model on an IBM SP. On 256 processors, the execution time was reduced by almost 30 percent without any changes to the original application source code. The proposed mapping approach is applicable to multiple programming models and distributed array management systems.