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VLDB '90 Proceedings of the 16th International Conference on Very Large Data Bases
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COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
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HPDC '00 Proceedings of the 9th IEEE International Symposium on High Performance Distributed Computing
THE SWIFT/RAID DISTRIBUTED TRANSACTION DRIVER
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IBM Systems Journal
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VLDB '05 Proceedings of the 31st international conference on Very large data bases
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ACM Transactions on Embedded Computing Systems (TECS)
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IEEE Communications Magazine
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We present a de-layered protocol engine for termination of 40Gbps TCP connections using a reconfigurable FPGA silicon platform. This protocol engine is designed for a planned attempt at the Internet Speed Record. In laboratory demonstrations at 40Gbps, this core beat the previous record of 7.2Gbps by a factor of five. We present an aggressive cross-layer optimization methodology and corresponding design-flow and tools used to implement this record-breaking TCP Protocol Engine.The 40Gbps TCP Offload Engine has been implemented on a Xilinx FPGA platform, based on a VirtexII-pro 2VP7 device. Each FPGA device terminates a 10Gbps OC-768 channel, and the aggregate capacity of the four FPGA devices is 40Gbps. The four 10Gbps channels are intended to be connected to four trunked 10GbE ethernet ports on a router. The 40Gbps TCP implementation has been demonstrated in the lab in system level as well as gate-level simulations, and live implementations have been tested with each 10Gbps channel FPGA board connected back-to-back in transmission tests at full wire-speed. We believe this to be the fastest TCP protocol engine to have been implemented so far.