The performance of multistage interconnection networks with finite buffers

Authors:
John D. Garofalakis;Paul G. Spirakis
Affiliations:
Computer Technology Institute, Patras, GREECE;Cow-ant Inst. Math. Sciences, NYU and Courant Inst. Math. Sciences, NYU
Venue:
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Year:
1990

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Abstract

Multistage interconnection networks with crossbar switches are a major component of parallel machines. In this paper we analyze Banyan networks of k by k switches and with finite buffers. The exact solution of the steady state distribution of the first stage is derived in the situation where packets are lost when they encounter a full buffer (Assumption A). The solution is a linear combination of k-1 geometrics. We use this to get an approximation for the steady state distributions in the second stage and beyond. As a side effect, the infinite buffer case is solved, confirming known results. Our results are validated by extensive simulations. An alternate situation of networks where full buffers may block previous switches is also analyzed through an approximation technique (Assumption B).