Energy-efficient and performance-enhanced disks using flash-memory cache
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Performance improvement of block based NAND flash translation layer
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
CPS-SIM: configurable and accurate clock precision solid state drive simulator
Proceedings of the 2009 ACM symposium on Applied Computing
A caching-oriented management design for the performance enhancement of solid-state drives
ACM Transactions on Storage (TOS)
A space reuse strategy for flash translation layers in SLC NAND flash memory storage systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Flash memory is widely adopted in various consumer products, especially for embedded systems. With strong demands on product designs for overhead control and performance requirements, vendors must have an effective design for the mapping of logical block addresses (LBA's) and physical addresses of data over flash memory. This paper targets such an essential issue by proposing a configurable mapping method that could trade the main-memory overhead with the system performance under the best needs of vendors. A series of experiments is conducted to provide insights on different configurations of the proposed method.