The design and implementation of a log-structured file system
ACM Transactions on Computer Systems (TOCS)
Configurable NAND Flash Translation Layer
SUTC '06 Proceedings of the IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing -Vol 1 (SUTC'06) - Volume 01
CFLRU: a replacement algorithm for flash memory
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
A superblock-based flash translation layer for NAND flash memory
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
Block recycling schemes and their cost-based optimization in nand flash memory based storage system
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
Modeling and simulating flash based solid-state disks for operating systems
Proceedings of the first joint WOSP/SIPEW international conference on Performance engineering
A flexible OS-based approach for characterizing solid-state disk endurance
Proceedings of the 9th conference on Computing Frontiers
Investigating hybrid SSD FTL schemes for Hadoop workloads
Proceedings of the ACM International Conference on Computing Frontiers
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NAND flash memory is the most widely used storage medium in embedded systems today due to its many advantages such as light weight, low power consumption, and shock resistance. Recently, solid state drives (SSDs), which use NAND flash memory to store data, are replacing conventional magnetic disks in laptops and some server computers. In the SSDs, to achieve both high performance and large capacity, a number of flash memory chips are connected to multiple buses and SSD firmware exploits parallel accesses by using interleaving and overlapping techniques. However, it is still unclear how many buses or chips should be used and how to drive those chips and buses to satisfy performance that may be required. To help answer these questions, we have developed a clock precision SSD simulator (CPS-SIM) that simulates the internal behavior of an SSD and that reports timing and utilization information. From the accurate timing and utilization results of CPS-SIM, we can discover the optimal hardware configuration including the number of buses and chips and their interconnections in an SSD. Also, it allows for fast development and verification of SSD firmware that runs an FTL (Flash Translation Layer) optimized for an SSD. Unlike FTLs for embedded flash memory, the FTL for an SSD must utilize the concurrency of the multiple chips and buses. By supporting concurrency, our CPS-SIM provides a flexible environment for design of SSD firmware that drives the multiple flash memory chips and also that schedules data transmissions via the multiple buses.