Low Power Digital CMOS Design
Logic-Level fast current simulation for digital CMOS circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Waveform coding for low-power digital filtering of speech data
IEEE Transactions on Signal Processing
| Hi-index | 0.00 |
This paper analyzes the power-area trade-off of functionally equivalent architectural implementations of a speech enhancement algorithm for hearing aids. Gate-level simulations and measurements show that an optimum degree of resource sharing (0.60mW in a 0.25μm CMOS process) is more energy-efficient than both the fully time-multiplexed (1.42mW) and the isomorphic architecture (1.54mW), without overly large area overhead (0.77mm2 against 0.43mm2 and 4.31mm2, respectively).