Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Engineering a simple, efficient code-generator generator
ACM Letters on Programming Languages and Systems (LOPLAS)
HDL optimization using timed decision tables
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Advanced compiler design and implementation
Advanced compiler design and implementation
ICSE '01 Proceedings of the 23rd International Conference on Software Engineering
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
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Compiling hardware models to machine code poses some unusual problems. While compilers for traditional programming languages are well understood, they tend to take very long to compile the C code generated from hardware models. The code generated from hardware models, unlike in the inputs seen by traditional compilers, have too many simple routines. These routines have much simpler control flow, and the patterns of the routines are repeated several times over. This paper discusses the approaches developed at Synopsys to compile these routines as optimally as traditional compilers, but taking less time.