Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
IEEE/ACM Transactions on Networking (TON)
Performance Analysis of Finite Buffered Multistage Interconnection Networks
IEEE Transactions on Computers
Design and analysis of a bandwidth management framework for ATM-based broadband ISDN
IEEE Communications Magazine
Journal of Computer Systems, Networks, and Communications
International Journal of Network Management
Future Generation Computer Systems
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This paper presents a novel architecture of internally two priority buffered Multistage Interconnection Network (MIN). First, we compare by simulation the new architecture against a single priority MIN and demonstrate up to N times higher throughput for the high priority traffic in a hot spot situation, when N is the number of inputs. In addition, under uniform traffic assumption we show an increase in the low priority throughput, without any change in the high priority throughput. Moreover, while in the single priority system the high priority delay and its standard deviation are increased when low priority traffic is present, it is kept constant in the dual priority system. Finally, we introduce a new approach of long Markovian memory performance model to better capture the packets dependency in a single priority MIN under uniform traffic and extend this model for a dual priority MIN. Model results are shown to be very accurate.