Winner-take-all networks of O(N) complexity
Advances in neural information processing systems 1
Silicon Implementation of Pulse Coded Neural Networks
Silicon Implementation of Pulse Coded Neural Networks
A Current-Mode Hysteretic Winner-take-all Network, with Excitatory and Inhibitory Coupling
Analog Integrated Circuits and Signal Processing
A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability
Analog Integrated Circuits and Signal Processing
Device Mismatch Limitations on the Performance of a Hamming Distance Classifier
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Implementations of artificial neural networks using current-mode pulse width modulation technique
IEEE Transactions on Neural Networks
A neuromorphic VLSI device for implementing 2D selective attention systems
IEEE Transactions on Neural Networks
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In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-驴m CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 驴s under 5-mV identified resolution. The input range is approximately to be rail-to-rail.