Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors

Authors:
Michael Freeman
Affiliations:
University of York, UK
Venue:
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Year:
2006

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Abstract

This paper describes the development of a FPGA based co-processor architecture for accelerating vector comparisons e.g. Euclidean distance. In this paper we will compare traditional pipelined and dataflow implementations, in terms of processing speed and area requirements. Processing performance will then be compared against a software implementation to evaluate possible speedup.