On the self-similar nature of Ethernet traffic (extended version)
IEEE/ACM Transactions on Networking (TON)
Operating system support for high-speed communication
Communications of the ACM
Lazy receiver processing (LRP): a network subsystem architecture for server systems
OSDI '96 Proceedings of the second USENIX symposium on Operating systems design and implementation
Effects of buffering semantics on I/O performance
OSDI '96 Proceedings of the second USENIX symposium on Operating systems design and implementation
Eliminating receive livelock in an interrupt-driven kernel
ACM Transactions on Computer Systems (TOCS)
ACM Transactions on Computer Systems (TOCS)
HIP: hybrid interrupt-polling for the network interface
ACM SIGOPS Operating Systems Review
Simulation Modeling and Analysis
Simulation Modeling and Analysis
EMP: zero-copy OS-bypass NIC-driven gigabit ethernet message passing
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
The APIC Approach to High Performance Network Interface Design: Protected DMA and Other Techniques
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
ATEC '96 Proceedings of the 1996 annual conference on USENIX Annual Technical Conference
Trapeze/IP: TCP/IP at near-gigabit speeds
ATEC '99 Proceedings of the annual conference on USENIX Annual Technical Conference
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Under heavy network traffic such as that of Gigabit Ethernet, interrupt-driven kernels can perform very poorly. Application processes can starve as CPU bandwidth of network hosts is consumed by the overhead involved in handling interrupts and processing incoming packets. The potential of having a high network bandwidth has little value in practice if no CPU power is left for applications to process or forward data. In addition, the system throughput can significantly be degraded, resulting in a receive-livelock condition. In this paper, we present analytical study of receive livelock and CPU utilization. We develop analytical models based on queueing theory and Markov processes. We consider and model three systems: ideal, PIO, and DMA. In an ideal system, the interrupt overhead is ignored. In PIO, DMA is disabled and the CPU performs copying of incoming packets. In DMA, copying of incoming packets is performed by DMA engines. Our analysis work can be valuable for engineering and designing certain system parameters. It becomes prudent to understand and predict how a host system behaves and performs when subjected to high network traffic. Good overload behaviour is critical. Simulations and reported experimental results show that our analytical models are valid and give an adequate approximation.