A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering

Authors:
Hidehiro Fujiwara;Koji Nii;Junichi Miyakoshi;Yuichiro Murachi;Yasuhiro Morita;Hiroshi Kawaguchi;Masahiko Yoshimoto
Affiliations:
Kobe University, Kobe, Japan;Kobe University, Kobe, Japan;Kobe University, Kobe, Japan;Kobe University, Kobe, Japan;Kanazawa University, Ishikawa, Japan;Kobe University, Kobe, Japan;Kobe University, Kobe, Japan
Venue:
Proceedings of the 2006 international symposium on Low power electronics and design
Year:
2006

Citing 3
Cited 0

Bus-invert coding for low-power I/O

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Narrow bus encoding for low power systems

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose a low-power two-port SRAM suitable for real-time video processing. In order to minimize discharge power on a read bitline, a majority-logic decides if input data are inverted in a write cycle, so that "1"s are in the majority. In video data, since more significant bits of adjacent pixel data are fortunately lopsided to either "0" or "1" with higher probability, the data bits in the pixels are reordered in each digit group to exploit the majority logic. The speed and area overheads are 4% and 11% in a 90-nm process technology, respectively. The proposed SRAM achieves 53% power reduction on the bitlines, and saves 43% of a total power when considered as an H.264 reconstructed-image memory.