A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application

Authors:
Yuichiro Murachi;Koji Hamano;Tetsuro Matsuno;Junichi Miyakoshi;Masayuki Miyama;Masahiko Yoshimoto
Affiliations:
The authors are with the Faculty of Engineering, Kanazawa University, Kanazawa-shi, 920-8667 Japan. E-mail: murachi@mics.ee.t.kanazawa-u.ac.jp,;The authors are with the Faculty of Engineering, Kanazawa University, Kanazawa-shi, 920-8667 Japan. E-mail: murachi@mics.ee.t.kanazawa-u.ac.jp,;The authors are with the Faculty of Engineering, Kanazawa University, Kanazawa-shi, 920-8667 Japan. E-mail: murachi@mics.ee.t.kanazawa-u.ac.jp,;The authors are with the Faculty of Engineering, Kobe University, Kobe-shi, 657-8501 Japan.;The authors are with the Faculty of Engineering, Kanazawa University, Kanazawa-shi, 920-8667 Japan. E-mail: murachi@mics.ee.t.kanazawa-u.ac.jp,;The authors are with the Faculty of Engineering, Kobe University, Kobe-shi, 657-8501 Japan.
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2005

Citing 0
Cited 2

A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering

Proceedings of the 2006 international symposium on Low power electronics and design
Novel video memory reduces 45% of bitline power using majority logic and data-bit reordering

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a 95 mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 1920 × 1080@30 fps resolution video. The search range is ±128 × ±64 pixels. The ME core integrates 2.25 M transistors in 3.1 mm × 3.1 mm using 0.18-micron technology.