A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs

  • Authors:
  • Jianwei Zhang;Yizheng Ye;Binda Liu

  • Affiliations:
  • Harbin Institute of Technology, Harbin, China;Harbin Institute of Technology, Harbin, China;National Cheng Kung University, Taiwan, China

  • Venue:
  • Proceedings of the 2006 international symposium on Low power electronics and design
  • Year:
  • 2006

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Abstract

A new mismatch-dependent low-power technique is presented for content-addressable memories (CAMs). With a novel shadow match-line voltage-detecting scheme, the word circuits realize fast self-disable of the charging paths in case of mismatches. Since the majority of CAMs words are mismatched, a significant power is reduced with a high search speed. Simulation results show the proposed 256-word-144-bit ternary CAM, using 0.13-?m 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900 ps search time. The achievement illustrates a 77% energy-delay-product (EDP) reduction as compared to the speed-optimized current-saving scheme.