Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
A taylor series methodology for analyzing the effects of process variation on circuit operation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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With the semiconductor industry pushing past the 65nm node and forward to 45nm and beyond, a host of phenomena are becoming prominent. For some time now, manufacturing variability and its impact on power and performance has captured the attention of the CAD research community, and is now transitioning to the commercial EDA market. Simultaneously, however, our ability to reliably predict the outcome of a semiconductor manufacturing process has been steadily deteriorating. This is happening because the rapidly increasing process complexity which is introducing a host of systematic sources of variation, as well as a natural increase in core random variability due to scaling. These factors increase the error in our performance predictions, and thus lead to a gap in model to hardware matching.In this tutorial, we will review the sources and impacts of model to hardware mismatch, and show examples of potential solutions to currently under development.