Effective Post-BIST Fault Diagnosis for Multiple Faults

  • Authors:

  • Hiroshi Takahashi;Shuhei Kadoyama;Yoshinobu Higami;Yuzo Takamatsu;Koji Yamazaki;Takashi Aikyo;Yasuo Sato

  • Affiliations:

  • Ehime University, Japan;Ehime University, Japan;Ehime University, Japan;Ehime University, Japan;Meiji University, Japan;Semiconductor Technology Academic Research Center (STARC);Semiconductor Technology Academic Research Center (STARC)

  • Venue:
  • DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
  • Year:
  • 2006

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Abstract

With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.