A Hardware Architecture for Integrated-Security Services
Transactions on Computational Science IV
An optimized hardware architecture for the montgomery multiplication algorithm
PKC'08 Proceedings of the Practice and theory in public key cryptography, 11th international conference on Public key cryptography
Design and implementation of real time secured RS232 link for multiple FPGA communication
Proceedings of the 2011 International Conference on Communication, Computing & Security
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The RSA algorithm is the standard for public-key cryptography today, with Montgomery multiplication [1] the most common mechanism of implementation due to modulo operations using a bitwise shift in place of a division operation. Several Montgomery designs have been proposed for ASIC and FPGA implementation based on limited resource availability to satisfy the computational burden [2,3,4]. FPGAs are now available that have large configurable logic resources in addition to dedicated high-speed ALU logic for operations such as multiplication. We propose an improvement to a limited resource Montgomery multiplier design, the MWR2MM algorithm proposed by Tenca and Koc, which is suitable for implementation on large FPGAs. The design can be scaled to utilize available FPGA multipliers, CLB logic and frequencies of operation.