FPGA Implementation of Genetic Algorithm for UAV Real-Time Path Planning
Journal of Intelligent and Robotic Systems
Implementation of a genetic algorithm on a virtex-ii pro FPGA
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
High-speed FPGA-based implementations of a genetic algorithm
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A genetic based disk scheduling method to decrease makespan and missed tasks
Information Systems
Hardware design of a new genetic based disk scheduling method
Real-Time Systems
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In this paper, we propose a technique to flexibly implement Genetic Algorithms (GAs) for various problems on FPGAs. For the purpose, we propose a common architecture for GA. The proposed architecture allows designers to easily implement a GA as a hardware circuit consisting of parallel pipelines which execute GA operations. The proposed architecture is scalable to increase the number of parallel pipelines. The architecture is applicable to various problems and allows designers to estimate the size of resulting circuits. We give a model for predicting the size of resulting circuits from given parameters. Based on the proposed method, we have implemented a tool to facilitate GA circuit design and development. Through experiments using Knapsack Problem and Traveling Salesman Problem (TSP), we show that the FPGA circuits synthesized based on the proposed method run much faster and consume much lower power than software implementation on a PC, and that our model can predict the size of the resulting circuit accurately enough.