Cache-conscious frequent pattern mining on modern and emerging processors

  • Authors:

  • Amol Ghoting;Gregory Buehrer;Srinivasan Parthasarathy;Daehyun Kim;Anthony Nguyen;Yen-Kuang Chen;Pradeep Dubey

  • Affiliations:

  • Department of Computer Science and Engineering, The Ohio State University, USA;Department of Computer Science and Engineering, The Ohio State University, USA;Department of Computer Science and Engineering, The Ohio State University, USA;Applications Research Laboratory, Corporate Technology Group, Intel Corporation, USA;Applications Research Laboratory, Corporate Technology Group, Intel Corporation, USA;Applications Research Laboratory, Corporate Technology Group, Intel Corporation, USA;Applications Research Laboratory, Corporate Technology Group, Intel Corporation, USA

  • Venue:
  • The VLDB Journal — The International Journal on Very Large Data Bases
  • Year:
  • 2007

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Abstract

Algorithms are typically designed to exploit the current state of the art in processor technology. However, as processor technology evolves, said algorithms are often unable to derive the maximum achievable performance on these modern architectures. In this paper, we examine the performance of frequent pattern mining algorithms on a modern processor. A detailed performance study reveals that even the best frequent pattern mining implementations, with highly efficient memory managers, still grossly under-utilize a modern processor. The primary performance bottlenecks are poor data locality and low instruction level parallelism (ILP). We propose a cache-conscious prefix tree to address this problem. The resulting tree improves spatial locality and also enhances the benefits from hardware cache line prefetching. Furthermore, the design of this data structure allows the use of path tiling, a novel tiling strategy, to improve temporal locality. The result is an overall speedup of up to 3.2 when compared with state of the art implementations. We then show how these algorithms can be improved further by realizing a non-naive thread-based decomposition that targets simultaneously multi-threaded processors (SMT). A key aspect of this decomposition is to ensure cache re-use between threads that are co-scheduled at a fine granularity. This optimization affords an additional speedup of 50%, resulting in an overall speedup of up to 4.8. The proposed optimizations also provide performance improvements on SMPs, and will most likely be beneficial on emerging processors.