Reusable models for timing and liveness analysis of middleware for distributed real-time and embedded systems

  • Authors:

  • Venkita Subramonian;Christopher Gill;César Sánchez;Henny B. Sipma

  • Affiliations:

  • Washington University, St. Louis, MO;Washington University, St. Louis, MO;Stanford University, Stanford, CA;Stanford University, Stanford, CA

  • Venue:
  • EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
  • Year:
  • 2006

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Abstract

Distributed real-time and embedded (DRE) systems have stringent constraints on timeliness and other properties whose assurance is crucial to correct system behavior. Formal tools and techniques play a key role in verifying and validating system properties. However, many DRE systems are built using middleware frameworks that have grown increasingly complex to address the diverse requirements of a wide range of applications. How to apply formal tools and techniques effectively to these systems, given the range of middleware configuration options available, is therefore an important research problem.This paper makes three contributions to research on formal verification and validation of middleware-based DRE systems. First, it presents a reusable library of formal models we have developed to capture essential timing and concurrency semantics of foundational middleware building blocks provided by the ACE framework. Second, it describes domain-specific techniques to reduce the cost of checking those models while ensuring they remain valid with respect to the semantics of the middleware itself. Third, it presents a verification and validation case study involving a gateway service, using our models.