RASCor: An associative hardware algorithm for real time stereo
Computers and Electrical Engineering
Measurement of Pedestrian Groups Using Subtraction Stereo
ISVC '09 Proceedings of the 5th International Symposium on Advances in Visual Computing: Part II
Robotic mapping and localization with real-time dense stereo on reconfigurable hardware
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Design and hardware implementation of a stereo-matching system based on dynamic programming
Microprocessors & Microsystems
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This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor (Pentium4@2 GHz), and is enough to generate a 3-D depth image at the video rate of 33 MHz.