Frequency-Scaling Approach for Managing Power Consumption in NOCs

  • Authors:

  • Chun-Lung Hsu;Wen-Tso Wang;Ying-Fu Hong

  • Affiliations:

  • The authors are with the Department of Electrical Engineering, National Dong Hwa University, Hualien, Taiwan, R.O.C. E-mail: cch@mail.ndhu.edu.tw;The authors are with the Department of Electrical Engineering, National Dong Hwa University, Hualien, Taiwan, R.O.C. E-mail: cch@mail.ndhu.edu.tw;The authors are with the Department of Electrical Engineering, National Dong Hwa University, Hualien, Taiwan, R.O.C. E-mail: cch@mail.ndhu.edu.tw

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2005

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Abstract

This work presents a frequency-scaling low-power (FSLP) design methodology for managing power consumption of cores in the tile-based network-on-chip (NOC) architecture. A moving picture experts group (MPEG) core is tested using the field-programmable gate array (FPGA) implementation to verify the feasibility of the proposed method. Measurement results show that about 30% power consumption can be saved in the MPEG core and reveal that the proposed FSLP design method can be suitable for cores in the tile-based NOC applications.