Low-Voltage Analog Switch in Deep Submicron CMOS: Design Technique and Experimental Measurements

  • Authors:

  • Christian Jésus B. Fayomi;Mohamad Sawan;Gordon W. Roberts

  • Affiliations:

  • The author is with Computer Science Department, Université du Québec à Montréal, Montreal, Canada. E-mail: cfayomi@ieee.org,;The author is with the Department of Electrical Engineering, Ecole Polytechnique de Montréal, Montreal, Canada.,;The author is with the Department of Electrical Engineering, McGill University, Montreal, Canada.

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2006

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Abstract

This paper concerns the design, implementation and subsequent experimental validation of a low-voltage analog CMOS switch based on a gate-bootstrapped method. The main part of the proposed circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. An important attribute of the design is that the ON-resistance is nearly constant. A test chip has been designed and fabricated using a TSMC 0.18 μm CMOS process (single poly, n-well) to confirm the operation of the circuit for a supply voltage of down to 0.65 V.