FPGA Acceleration of RankBoost in Web Search Engines
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A packet-switched network architecture for reconfigurable computing
ACM Transactions on Embedded Computing Systems (TECS)
A special-purpose architecture for solving the breakpoint median problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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High-Performance Reconfigurable Computers (HPRCs) based on the combination of conventional processors and FPGAs have been gaining attention in the past few years. Their benefits were particularly harnessed in compute-intensive integer applications. However, there has been doubt that the same benefits can be attained for general scientific applications. Fortunately, the trend in reconfigurable chip sizes and diversity of resources may be relieving some of those concerns. Yet, with the hardware reconfigurability, it is feared that domain scientists have to learn how to design hardware if they were to use such machines effectively. In order to address the overarching question, this panel will address the following questions: Can FPGAs deliver order-of-magnitude performance gains in scientific floating-point applications in the foreseeable future? Can programming HPRCs programmability become similar to that of HPCs in its level of difficulty? What are the major developments in the industry or the community that make all this possible?