Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
The network architecture of the Connection Machine CM-5 (extended abstract)
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Performance Evaluation of Switch-Based Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Adaptive Source Routing in Multistage Interconnection Networks
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Experience with active messages on the Meiko CS-2
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
Exploring pattern-aware routing in generalized fat tree networks
Proceedings of the 23rd international conference on Supercomputing
Fast pattern-specific routing for fat tree networks
ACM Transactions on Architecture and Code Optimization (TACO)
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This paper presents an efficient hardware architecture for scheduling connections on a fat-tree interconnection network for parallel computing systems. Our technique utilizes global routing information to select upward routing paths so that most conflicts can be resolved. Thus, more connections can be successfully scheduled compared with a local scheduler. As a result of applying our technique to two-level, three-level and four-level fat-tree interconnection networks of various sizes in the range of 64 to 4096 nodes, we observe that the improvement of schedulability ratio averages 30% compared with greedy or random local scheduling. Our technique is also scalable and shows increased benefits for large system sizes.