Coverage-driven automatic test generation for uml activity diagrams
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A formal verification framework for SysML activity diagrams
Expert Systems with Applications: An International Journal
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The UML Activity Diagram language is the de facto language for behavioral modeling capable of block level modeling of real time multiprocessor SoC applications where timing behavior is a critical aspect. Although there are several tools for timing verification of logics with branching time semantics, there are no known model checkers for timing verification of logics with linear time semantics as needed for many verification tasks. This work deals with timing verification of UML Activity Diagram models of applications. We propose a subset of TPTL (Timed Propositional Temporal Logic) for specifying timing queries. We develop an automata based model checker for verifying such queries. We present a comparison of the proposed timing verification with the state of the art for random testcases.