Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
The Journal of Supercomputing
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The FPGA (Field Programmable Gate Array) strikes a middle ground in cost/power/performance between ASIC (Application Specific Integrated Circuit) and DSP (Digital Signal Processor), while providing field programmability via reconfiguration of internal interconnect and logic functions. However, most current FPGA-based solutions are highly specialized hardware systems designed for narrowly focused dedicated applications. These systems are typically programmed with low-level hardware description languages (HDL) inherited from ASIC design methodologies. The lack of high-level, user-friendly programming models and modular scalable reusable hardware system architectures is the key factor impeding wider adoption of large-scale FPGA-based system. In this thesis, we have demonstrated the practical application of a new generation of high-end reconfigurable computer (HERC) systems that were built with FPGAs as the sole processing element. Through the design and construction of two generations of the Berkeley Emulation Engine (BEE) systems, a high-level, user-friendly software programming model based on synchronous data flow was developed to provide an efficient and productive design methodology for a wide range of high-performance DSP applications and emulation of wireless communications systems. To date, multi-antenna radio astronomy signal processing has provided the largest-scale application of the BEE2 system. We have successfully demonstrated an 800MHz, billion-channel spectrometer using the BEE2 system on a single antenna, as well as a four-antenna 150MHz imaging correlator. Each BEE2 module provided sustained performance up to 1 trillion integer operations per second, and the BEE2 served as the basic building block for larger-scale systems with one to hundreds of modules. In terms of computational throughput per chip, the FPGAs in the BEE2 system outperform a 720MHz (130nm) DSP by a factor of 10 to 34, a 1 GHz (90nm) DSP by a factor of 7 to 25, and the latest Pentium-4 by a factor of 4 to 13. In terms of power efficiency, the XC2VP70 FPGA delivers 72% to 106% more throughput on 16-bit operations compared to DSPs, and more than 1100% more throughput on 4-bit operations. When compared to microprocessors, the FPGA proved over 100 times more power-efficient. Similarly, the compute throughput per unit chip cost of FPGAs is 20% to 307% more than the 1 GHz DSP, and 50% to 505% more than the 3.8GHz Pentium-4 processor. Combining DSP-like ease of programming, ASIC-like computational efficiency, and the scalability of computer clusters, the BEE2 system is becoming a preferred solution for a variety of high-performance digital signal processing applications. With continued evolution of hardware architecture and improvements in alternative programming models, future generations of HERC systems will serve as general-purpose computing platforms for many additional application domains, including scientific computing and computational biology.