Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
Low-power architectural design methodologies
Low-power architectural design methodologies
WSC '96 Proceedings of the 28th conference on Winter simulation
MRE: a flexible approach to multi-resolution modeling
Proceedings of the eleventh workshop on Parallel and distributed simulation
Parallel mixed-level power simulation based on spatio-temporal circuit partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dynamic component substitution in web-based simulation
Proceedings of the 32nd conference on Winter simulation
Optimizing Costs of Web-based Modeling and Simulation
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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High resolution models of logic circuits need to be used in simulations to accurately track logic transitions or glitches, which contribute to the most dominant portion of VLSI power dissipated. Unfortunately, simulating large, high resolution models is a time consuming task. Although more abstract models that simulate faster can be used, they are less accurate as details of glitching activity are absent. This study proposes an alternatively approach that dynamically (i.e., during simulation) changes the resolution of a model to strike a better balance between accuracy and performance. Simulation-time resolution changes are performed using a novel methodology called Dynamic Component Substitution (DCS). This paper presents the issues involved in applying DCS to accelerate parallel power simulations of digital logic circuits. The experiments indicate that the proposed strategy can increase performance by 3x with negligible deviations in power estimates but consuming about 2x more memory.