Area efficient loop filter design for charge pump phase locked loop

  • Authors:

  • Raghavendra R G;Bharadwaj Amrutur

  • Affiliations:

  • Indian Institute of Science, Bangalore, India;Indian Institute of Science, Bangalore, India

  • Venue:
  • Proceedings of the 17th ACM Great Lakes symposium on VLSI
  • Year:
  • 2007

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Abstract

In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop(CPPLL). The proposed circuits were designed in 0.25μ CSM analog process with 1.8V supply. The proposed circuits achieved up to 85% savings in capacitor area. Simulations showed good match of the new circuits with the conventional circuit. The proposed circuits are particularly useful in applications that demand low die area.