Latency hiding through multithreading on a network processor

Authors:
Xiaofeng Guo;Jinquan Dai;Long Li;Zhiyuan Lv;Prashant R. Chandra
Affiliations:
Intel Asia-Pacific Research & Development Ltd., Shanghai, China;Intel Asia-Pacific Research & Development Ltd., Shanghai, China;Intel Asia-Pacific Research & Development Ltd., Shanghai, China;Intel Asia-Pacific Research & Development Ltd., Shanghai, China;Intel Corporation, Santa Clara, CA
Venue:
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
Year:
2007

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