Deterministic and statistical admission control for QoS-Aware embedded systems

  • Authors:
  • Jungkeun Park;Minsoo Ryu;Seongsoo Hong

  • Affiliations:
  • School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea (Corresponding author. E-mail: jkpark@redwood.snu.ac.kr);College of Information and Communications, Hanyang University, Seoul 133-791, Korea;School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea

  • Venue:
  • Journal of Embedded Computing - Real-Time and Embedded Computing Systems
  • Year:
  • 2005

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Abstract

This paper presents two classes of admission control schemes for embedded system applications that have real-time constraints but with composite characteristics in request arrivals and resource requirements. First, we present admission control tests using utilization demands to handle a mix of periodic and aperiodic tasks with deterministic execution times. The utilization demand is defined as the processor utilization required for a task to meet its deadline with certainty, thus for deterministic deadline guarantees. We show that the use of utilization demands eliminates the need for complicated schedulability analysis and enables on-line admission control. Second, we present statistical admission control schemes using effective execution times to handle stochastic execution times. Effective execution times are determined from the specified probability demanded by the application and stochastic properties of task execution times. Every task is associated with an effective execution time and is restricted to using processor time not exceeding its effective execution time. This scheme allows every task to meet its deadline with the specified probability without being interfered with, and greatly simplifies the admission control when combined with utilization demands. Our experimental results confirm the correctness of the proposed approaches. They also show that our admission tests are very accurate to achieve high-level processor utilization.