A data cache with multiple caching strategies tuned to different types of locality
ICS '95 Proceedings of the 9th international conference on Supercomputing
A modified approach to data cache management
Proceedings of the 28th annual international symposium on Microarchitecture
Run-time adaptive cache hierarchy management via reference analysis
Proceedings of the 24th annual international symposium on Computer architecture
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Utilizing reuse information in data cache management
ICS '98 Proceedings of the 12th international conference on Supercomputing
Cache-conscious data placement
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Cache-conscious structure layout
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Cache-conscious structure definition
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
IEEE Transactions on Computers
Region-based caching: an energy-delay efficient memory architecture for embedded processors
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Computation offloading to save energy on handheld devices: a partition scheme
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
The hardness of cache conscious data placement
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
The Minimax Cache: An Energy-Efficient Framework for Media Processors
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Optimal Replacement Is NP-Hardfor Nonstandard Caches
IEEE Transactions on Computers
A sample-based cache mapping scheme
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
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Embedded processors such as the Intel StrongARM SA-1110 and the Intel XScale utilize multiple caches at the same level in the cache hierarchy. The main cache and the mini-cache differ in both the size and the associativity. Furthermore, the processors allow programs to specify the cache mapping policy for each virtual page among three choices, i.e. whether to map the page to the main cache, the mini-cache, or neither. In the latter case, the page is marked as noncacheable. In this paper, we investigate the problem of optimal cache mapping, assuming that we can predict the trace of the memory reference in advance. On the theoretical side, we prove that the problem of finding the optimal cache mapping for an arbitrary memory trace is NP-hard. On the experimental side, we present a mapping heuristic and compare the result with the default policy which maps all pages to the main cache. Our measurement shows that, compared to the default policy, the heuristic can reduce the execution time from 1% to 21% for a set of test programs. As a byproduct of performance enhancement, we also save the energy by 4% to 28%.