Two novel shared-clock scheduling algorithms for use with 'Controller Area Network' and related protocols

Authors:
Devaraj Ayavoo;Michael J. Pont;Michael Short;Stephen Parker
Affiliations:
Embedded Systems Laboratory, University of Leicester, University Road, Leicester LE1 7RH, UK;Embedded Systems Laboratory, University of Leicester, University Road, Leicester LE1 7RH, UK;Embedded Systems Laboratory, University of Leicester, University Road, Leicester LE1 7RH, UK;Pi Technology, Milton Hall, Ely Road, Milton, Cambridge CB4 6WZ, UK
Venue:
Microprocessors & Microsystems
Year:
2007

Citing 4
Cited 5

Patterns for time-triggered embedded systems: building reliable applications with the 8051 family of microcontrollers

Patterns for time-triggered embedded systems: building reliable applications with the 8051 family of microcontrollers
Non-preemptive scheduling of messages on controller area network for real-time control applications

RTAS '95 Proceedings of the Real-Time Technology and Applications Symposium
Designing embedded systems using patterns: a case study

Journal of Systems and Software - Special issue: Computer systems
Analysis of channel utilization for controller area networks

Computer Communications

Assessment of high-integrity embedded automotive control systems using hardware in the loop simulation

Journal of Systems and Software
Full length Article: A generic controller architecture for intelligent robotic systems

Robotics and Computer-Integrated Manufacturing
Erratum: Comments on: "Two novel shared-clock scheduling algorithms for use with 'Controller Area Network' and related protocols"

Microprocessors & Microsystems
A fuzzy predictive redundancy system for fault-tolerance of x-by-wire systems

Microprocessors & Microsystems
Improving flexibility and fault-management in CAN-based "Shared-Clock" architectures

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The Controller Area Network (CAN) protocol is widely employed in the development of distributed embedded systems. Previous studies have illustrated how a ''Shared-Clock'' (S-C) algorithm can be used in conjunction with CAN-based microcontrollers to implement time-triggered network architectures. This study explores some limitations of the existing S-C algorithms (''TTC-SC1'' and ''TTC-SC2''), and introduces two new algorithms (''TTC-SC3'' and ''TTC-SC4''). The results presented in the paper suggest that TTC-SC3 and TTC-SC4 are useful additions to the range of shared-clock algorithms.