Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium® architecture

Authors:
Arun Kejariwal;Gerolf F. Hoflehner;Darshan Desai;Daniel M. Lavery;Alexandru Nicolau;Alexander V. Veidenbaum
Affiliations:
University of California, Irvine;Intel Corporation;Intel Corporation;Intel Corporation;University of California, Irvine;University of California, Irvine
Venue:
Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Year:
2007

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Abstract

Recently SPEC1 released the next generation of its CPU benchmark, widely used by compiler writers and architects for measuring processor performance. This calls for characterization of the applications in SPEC CPU2006 to guide the design of future microprocessors. In addition, it necessitates assessing the change in the characteristics of the applications from one suite to another. Although similar studies using the retired SPEC CPU benchmark suites have been done in the past, to the best of our knowledge, a thorough characterization of CPU2006 and its comparison with CPU2000 has not been done so far. In this paper, we present the above; specifically, we analyze IPC (instructions per cycle), L1, L2 data cache misses and branch prediction, especially in CPU2006.