FPGA implementation of QR decomposition using MGS algorithm
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
| Hi-index | 0.00 |
This paper presents a novel architecture mapping technique which was essential in the design of a QR array which forms the core processor of a single chip adaptive beamforming system. The mapping technique assigns a QR triangular array of 2m/sup 2/+3m+1 cells down onto a linear architecture of m+1 processors. The mapping results in a linear systolic architecture with one hundred percent hardware utilisation, local interconnects and individual processors for boundary and internal cell operations. In addition, this paper highlights the effect latency has on the validity of the linear architecture.