An improved approach to fault tolerant rank order filtering on a SIMD mesh processor
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Rank Order Filtering on an Array with Faulty Processors
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
| Hi-index | 0.01 |
This paper examines a fault tolerant scheme for two-dimensional arrays of processors which functionally reconfigures the array without the use of spares. Reconfiguration approaches for different interconnection networks are analyzed. Also, three approaches are proposed for mapping image data to and from the array, depending on the type of array and computational power available in each processing element. The proposed reconfiguration approaches have been emulated on a 32x64 processor MasPar array computer.