Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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In networks-on-chip (NoC) designs, delay variations and crosstalk noise have become a serious issue with the continuously shrinking geometry of semiconductor devices and the increasing switching speed. The crosstalk between adjacent lines causes data dependent signal delay and noise, thus finally makes the communication channel unreliable. The crosstalk problem can be mitigated by wide spacing of serial lines, however, the wider spacing of serial lines will reduce the number of the lines, thus reduce the data throughput. In this paper, we propose a multi-path routing scheme to maximize the data throughput by utilizing multiple paths for concurrent data transmission. For the proposed multi-path routing scheme, we consider two transport models: the multi-path full bitbank transport model and the multi-path half bitbank transport model. Through theoretical analysis, we show that the proposed multi-path scheme achieves significant improvement in data throughput under both transport models.