A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations

Authors:
Sarvesh Bhardwaj;Sarma Vrudhula
Affiliations:
Arizona State University, Tempe, AZ;Arizona State University, Tempe, AZ
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Voltage and temperature aware statistical leakage analysis framework using artificial neural networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

This paper presents an accurate and efficient approach for estimating the full chip leakage in the presence of intra-die variations. We use an accurate model for leakage in which the leakage is exponentially dependent on a quadratic function of the device parameters. The intradie correlations in the device parameters are accounted by representing the parameters in terms of abstract independent random variables using Karhunen-Lo`eve Expansion. The total circuit leakage is computed using an efficient sum operation. Our results on ISCAS89 benchmark circuits show a speed up of up to 500脳 compared to Monte Carlo analysis, with average percentage difference in mean and variance being less than 1.5%.