Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits

Authors:
Srinath R. Naidu
Affiliations:
Magma Design Automation India Pvt. Ltd., Bangalore, India
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Statistical static timing analysis: A survey

Integration, the VLSI Journal

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Abstract

This paper presents a pair of novel techniques to speed-up path-based Monte-Carlo simulation for statistical timing analysis of digital integrated circuits with no loss of accuracy. The presented techniques can be used in isolation or they could be used together. Both techniques can be readily implemented in any statistical timing framework. We compare our proposed Monte-Carlo simulation with traditional Monte-Carlo simulation in a rigourous framework and show that the new method is up to 2 times as efficient as the traditional method.