Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

Authors:
T. Sansaloni;A. Pérez-Pascual;V. Torres;J. Valls
Affiliations:
Department of Electronic Engineering, Polytechnic University of Valencia, Grao de Gandía, Spain 46730 and Department of Electronic Engineering, Polytechnic University of Valencia, Grao de Gan ...;Department of Electronic Engineering, Polytechnic University of Valencia, Grao de Gandía, Spain 46730;Department of Electronic Engineering, Polytechnic University of Valencia, Grao de Gandía, Spain 46730;Department of Electronic Engineering, Polytechnic University of Valencia, Grao de Gandía, Spain 46730
Venue:
Journal of VLSI Signal Processing Systems
Year:
2007

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Abstract

A scheme for reducing the hardware resources to implement on LUT-based FPGA devices the twiddle factors required in Fast Fourier Transform (FFT) processors is presented. The proposed scheme reduces the number of embedded block RAM for large FFTs and the number of slices for FFT lengths higher than 128 points. Results are given for Xilinx devices, but they can be generalized for other advanced LUT-based devices like ALTERA Stratix.