Analog design for reuse - case study: very low-voltage sigma-delta modulator
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
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Design of low-voltage high-resolution MOSFET-only pipeline analog to digital converters (ADCs) has been investigated in this work. The nonlinearity caused by replacing linear MIM capacitors with compensated depletion-mode MOS transistors in all 1.5-bit residue stages of the ADC has been properly modeled to be calibrated in digital domain. The proposed calibration technique makes it possible to digitally compensate the nonlinearity of a 1.8V 12-bit 65MS/s MOSFET-only ADC in 0.18μm standard digital CMOS technology. It improves the values of signal-to-noise-plus-distortion-ratio (SNDR) and spurious-free dynamic range (SFDR) by approximately 27dB and 35dB respectively.