Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Fault-Robust Microcontrollers for Automotive Applications
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Analysis of system bus transaction vulnerability in systemC TLM design platform
CEA'09 Proceedings of the 3rd WSEAS international conference on Computer engineering and applications
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This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the IEC 61508, an international norm for the functional safety of electronic safety-related systems, of which an overview is given in the paper. The methodology is based on a theory to decompose a digital circuit in "sensible zones" and a tool that automatically extracts these sensible zones from the RTL description. It includes as well a spreadsheet to compute the metrics required by the IEC norm such Diagnostic Coverage and Safe Failure Fraction. The FMEA results are validated by using another tool suite including a fault injection environment. The paper explains how to take benefits of the information provided by such approach and as example it is described how the methodology has been applied to design memory sub-systems to be used in fault robust microcontrollers for automotive applications. This methodology has been approved by TÜV-SÜD as the flow to assess and validate the Safe Failure Fraction of a given SoC in adherence to IEC 61508