Statistical static timing analysis: A survey
Integration, the VLSI Journal
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An increasing demand for higher performance, lower power density, and greatly expanded functionalities will deter-mine radical changes in the future computing architectures. These widely acknowledged emerging trends are however insufficient to address all the challenges introduced by advanced silicon nanome-ter technologies. It is well known that manufacturability for high yield, along with design productivity and predictability are major problems in gigascale System-on-Chip (SoC) design. Moreover, as technology advances deeper into the nanometer regime, a tight control on process parameters is increasingly difficult. As a con-sequence, variability will be a dominant factor in the design of complex ICs that must be addressed at the technology, circuit, and architecture level. In this talk, we will discuss the impact of sys-tematic and random variations, and we will present a new archi-tecture-to-silicon design platform based on the concept of regular-ity at different levels of abstraction. Moreover, we will also intro-duce an innovative design methodology to synthesize clockless circuits, which can be exploited to implement logic blocks that operate under process, power supply, and temperature variations.