A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

  • Authors:

  • Tan Kok-Siang;Mohd-Shahiman Sulaiman;Mamun Reaz;Chuah Hean-Teik;Manoj Sachdev

  • Affiliations:

  • VLSI Research Group, Faculty of Engineering, Multimedia University, Cyberjaya, Malaysia 63100;VLSI Research Group, Faculty of Engineering, Multimedia University, Cyberjaya, Malaysia 63100;VLSI Research Group, Faculty of Engineering, Multimedia University, Cyberjaya, Malaysia 63100;VLSI Research Group, Faculty of Engineering, Multimedia University, Cyberjaya, Malaysia 63100;Department of Electrical & Computer Engineering, University of Waterloo, Waterloo, Canada N2L3G1

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2007

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Abstract

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 μm CMOS process and occupies an active area of 0.2 脳 0.32 mm2. The CDR exhibits an RMS jitter of 卤 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.