Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
DOP: a CPU core for teaching basics of computer architecture
WCAE '03 Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer Architecture
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
An emulated computer with assembler for teaching undergraduate computer architecture
WCAE '05 Proceedings of the 2005 workshop on Computer architecture education: held in conjunction with the 32nd International Symposium on Computer Architecture
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Students who are beginners face difficulties in understanding basics of Computer Architecture. Their problems have been identified, and a project has been initiated to address these problems, with defined objectives. The project is to be implemented in stages: design a processor; build a simulator; develop a compiler and develop an intergraded system. The paper presents the results of the first stage -- design a processor. The features and characteristics of the processor are defined and the design process is described in detail. The SEP (Students' Experimental Processor) integrates different types of architectures: Memory-Memory, Accumulator, Extended Accumulator, Stack, Register Memory, and Load Store. It can be switched to any one of them. It was modeled using VHDL and is ready to be implemented on FPGAs. The SEP will support the introductory level students to understand the characteristics of computer architectures and their operations. Future developments of Computer Architecture education using the processor are also discussed.