A computer architecture education curriculum through the design and implementation of original processors using FPGAs

Authors:
Yutaka Sugawara;Kei Hiraki
Affiliations:
University of Tokyo, Bunkyo-ku, Tokyo, Japan;University of Tokyo, Bunkyo-ku, Tokyo, Japan
Venue:
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
Year:
2004

Citing 6
Cited 1

Computer architecture (2nd ed.): a quantitative approach

Computer architecture (2nd ed.): a quantitative approach
Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1

MSE '99 Proceedings of the IEEE International Conference on Microelectronic Systems Education
Hands-on computer architecture: teaching processor and integrated systems design with FPGAs

WCAE '00 Proceedings of the 2000 workshop on Computer architecture education
Using custom hardware and simulation to support computer systems teaching

WCAE '02 Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture
On the design of a new CPU architecture for pedagogical purposes

WCAE '02 Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture
On the introduction of reconfigurable hardware into computer architecture education

WCAE '03 Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer Architecture

Students' experimental processor: a processor integrated with different types of architectures for educational purposes

WCAE '06 Proceedings of the 2006 workshop on Computer architecture education: held in conjunction with the 33rd International Symposium on Computer Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present the new curriculum of the processor laboratory of the Department of Computer Science at the University of Tokyo. This laboratory is a part of the computer architecture education curriculum. In this laboratory, students design and implement their own processors using field-programmable gate arrays (FPGAs), and write the necessary software. In 2003, the curriculum of the laboratory was changed, the main change being that the FPGA was changed to a large one to increase the range of design trade-offs. As a result, students have been enabled to implement the techniques used in modern processors such as FPU, cache, branch prediction, and superscalar architecture. In this paper, we detail the new curriculum and note the educational results of the year following the changes. Especially, we focus on the educational advantages of the large FPGA size.