ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A Design Methodology for Matching Improvement in Bandgap References
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
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To mitigate the impact of fabrication process in the performance of Bandgap Voltage References (BGR) usually a trim circuit is included. This technique results in more die area and longer test times. Reducing the trim range reduces the area overhead and test time. Other factor that can also limit the performance of BGR circuits is the output noise, generated by integrated devices or from the supply voltage. This work studies how the output noise and variability due to process variations can impact the design and applicability of the trim circuit. For this proposal, three BGR 's were designed in a commercial 0.35 µm CMOS technology. Results show that in high-order BGR's, where the output noise is more relevant, the output noise must be properly accounted for in the design of the BGR and trim circuit. This leads to reduced trim range and proper prediction of the maximum precision that can be achieved.