A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Parameters Adjusting of Third-Order PLL Used in LEO Mobile Satellite Communication Systems
AINA '03 Proceedings of the 17th International Conference on Advanced Information Networking and Applications
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This paper presents the project and implementation results of a digital PM demodulator system for processing LEO satellite signals from Brazilian Data Collecting System. The demodulator was implemented on the Altera Cyclone II DSP Development Kit equipped with FPGA EP2C70. Demodulation is done with a second order Digital Phase Locked Loop (DPLL) with -π to π linear phase detector realized by a CORDIC algorithm operating on vectoring mode. The parameters of the DPLL were calculated using control system theory.