A VHDL primer (3rd ed.)
Designing Run-Time Reconfigurable Systems with JHDL
Journal of VLSI Signal Processing Systems
Compiling Image Processing Applications to Reconfigurable Hardware
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Cameron: High Level Language Compilation for Reconfigurable Systems
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Flowchart techniques for structured programming
ACM SIGPLAN Notices
A Novel Approach to Real-time Bilinear Interpolation
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
User evaluation and overview of a visual language for real time image processing on FPGAs
Proceedings of the 10th International Conference NZ Chapter of the ACM's Special Interest Group on Human-Computer Interaction
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Real-time video processing is an image-processing application that is ideally suited to implementation on FPGAs. We discuss the strengths and weaknesses of a number of existing languages and hardware compilers that have been developed for specifying image processing algorithms on FPGAs. We propose VERTIPH, a new multiple-view visual language that avoids the weaknesses we identify. A VERTIPH design incorporates three different views, each tailored to a different aspect of the image processing system under development; an overall architectural view, a computational view, and a resource and scheduling view.